I have a weird issue with MKR Vidor 4000. It appears that tiny designs fail to start, or maybe are flashed incorrectly.
I follow a standard practice - build the fpga design, convert the output .ttf file to app.ttf and signature.h with makeCompositeBinary program, include those in library and build the sketch. I don't get any issues with the programming process itself, the progress steadily goes up to 100%, the cpu gets reset and sketch starts. With debug messages printed through serial port I get indication that the fpga was initialized, but I don't see the test signals on the pins.
Trying to upload other designs known to work earlier (VidorGraphics), I noticed that if I upload my tiny design after the large VidorGraphics, I still have video output, like if my design did not replace the VidorGraphics. The screen gets occasional black dots appearing across the image, like if the Nios firmware was damaged and it's running a garbage code. Feels almost like my tiny design gets flashed at the beginning of the configuration stream, but fpga continues to read the stream past the end of my design, so basically gets configured with previous design, "patched" with my tiny "addition" at the beginning.
In Vidor templates projects the stream compression is turned on, this gives very small configuration streams on simplistic designs. So I've produced another .ttf file by converting .sof to .ttf but without compression. The resulting ttf is now as large as the one from VidorGraphics. Flashing this stream now finally gives me the output signals I expect to see, indicating the fpga was properly configured.
So now I don't get it, is it fpga not stopping configuration at the end of the smaller stream, maybe because the stream should end with some marker that is not there, or maybe bossac/bootloader not erasing properly the area for config stream, or cutting something early?
What could be the workarounds, other than aiming for huge stream files? Explicitly padding the .ttf with 0xff to mimic erased flash?