Help debugging circuit

Warning: For anyone who started reading, the schematic below is wrong. Hopefully right one is in post #15.

Hi, I finally received the boards from here and tried to set up my deep-sleep/external wakeup ESP8266 (Wemos D1 Mini).
Unfortunately, I have a problem I cannot explain. Here is the reset schematic:

rst.png

Note that RST has an internal pullup of 10k in the Wemos D1, which I put on the breadboard in the photo for the test.
Note also that D3 also has a pullup of 10k in the Wemos D1, which I soldered on the PCB to open the transistor.

I tested the cap in the detached circuit to be 8.64µF, and the resistance comes up to infinite.

Still, as you can see in the photo, if I connect D0 to GND, the RST voltage drops to something like 0.65V (confirmed with multimeter, its not the shitte “oscilloscope”).
I cannot explain how that can happen. The cap should only let a pulse through, but it just stays at almost GND. A fully set up version works with internal wake up, because it already creates a pulse at D0, but if I use an external wake up that stays low, RST also stays low and the ESP doesn’t boot.

The idea is that wake up pulses can come both from the wake-up timer at D0 or an external switch that is supposed to be able to stay open while the ESP runs (hence the cap). D3 can be used to disable the RST feature to avoid reboots while the ESP is running.

Photos of circuit:
https://cloud.voits.net/index.php/s/ov0ymp0fO3KYEcN
https://cloud.voits.net/index.php/s/KO0u9t0tMmU4DYc
(Perhaps someone could have a look, why I am not able to attach these. Allegedly, they fail a “security test”).

Images :

Your link open a page on next cloud, on that page right click on image and choose “Copy image link” and paste that in your post.

Ciao, Ale.

Thanks. I tried that in another post but for some reason, they break once in a while. Let's see if that happens here, too.

Ok, I tested a little more. All I tested seemed normal, except for the voltage at the emitter. At 3.3 V cuircuit voltage, it reads something like 2.9 in equilibrium. If I ground it, goes to 0, of course. If I remove GND, it immediatly shoots to 3.1-3.3V, then slowly (1s+) drops to 2.9V. What is going on?

OK, stupid me, that is the drop over the transistor. I was confused about the slow drop, but that is actually the train over the voltmeter/oscilloscope. If I attach the measurement device later, it will still capture the drop, so there is nothing wrong on the pcb, as far as it seems.

But still: As soon as I ground D0, RST goes to 0.68V and stays at that value. As soon as I unconnect D0, it goes back to 3.3V again.

Again: on an unconnected board:

  • R D0-Emitter: Infinite (Cap blocks DC)
  • R D0-3.3VPin: 100.3kOhm (R1 fine)
  • C D0-Emitter:8.4µF, if my multimeters COM is on RST. No reading ("0.LµF"), if COM is at the emitte, because then there is a short circuit over the pullups and base and emitter of the NPN.

So, everything reads fine, as far as I can see. How can D0 permanently overcome the pullup at RST???

I would try to :

  • lower the value of the cap (0.1 - 1 uF)

  • if D0 already give an appropriate pulse, cap is not needed there, so move it to the PB side.

Ciao, Ale.

The problem is your resistors. They are not 100K and 1K respectively. I can tell from the color bands on the resistors in the pictures you posted. Replace them with correct resistors and it should work fine.

ilguargua:
I would try to :

  • lower the value of the cap (0.1 - 1 uF)

  • if D0 already give an appropriate pulse, cap is not needed there, so move it to the PB side.

Ciao, Ale.

Do you have any theory why this should cause my problem? Because I don't have one.

  • The cap is chosen according to a prior breadboard test. 0.1µ was not enough. While 1µ could still work, this shouldn't cause the problem at all.
  • D0 is supposed to double as a sensing pin for the external trigger. Again, I don't see how this should change anything. Keep in mind that I don't have the ESP in there, yet, just the pullups that would be there. So no complicated interference from that side to be expected.

The problem is your resistors. They are not 100K and 1K respectively. I can tell from the color bands on the resistors in the pictures you posted. Replace them with correct resistors and it should work fine.

The resistors you mention are not banded at all, they are SMD. The banded ones you see are the ones that would be the pullups, if a D1 would be in place. The one on the breadboard has the correct value of 10k. The one soldered in has 5.7k (D1 would be 10k again), but I don't see how this would cause the problem. This provides the base current, and I know that works, because as soon as I unconnect D0 from GND, the emitter goes to 3.3V again, so I get current from the emitter.
Also, as far as I can see, RST has a pullup and is completely DC-isolated agaonst D0 with the cap, no wrong resistor value in the world should make it stay low when D0 is low.

ElCaron:
The resistors you mention are not banded at all, they are SMD. The banded ones you see are the ones that would be the pullups, if a D1 would be in place.

Ok, that wasn’t clear in your previous posts. I’d say there is something wrong with your voltage divider. Maybe you misread the resistance values or something. Can you check them with a DMM?

Also, I wouldn’t change the cap placement or the value (in your case, the higher the better), but be aware that using a cap will cause your circuit to have a highpass filter frequency response.

Just to be absolutely clear, what EXACTLY is this supposed to do? What are the inputs, what are the outputs, what is the P1 connector supposed to be, etc? I’m not familiar with the whole deep sleep thing, but I can help analyze your circuit better if you explain it.

I already measured almost all values and posted the results above. I think the only one I did not post is the 1k, but I see no way any wrong value there can cause an issue.

The circuit is for controlling the wake-up of a deep-sleep ESP 8266 via LOW pulses to the RST pin (the common way to wake up a deep-sleep ESP).

ESP on:
D3 is set to output LOW, isolating RST from the circuit so that the ESP cannot be reset. RST is stabilized by the internal 10k pullup.
D0 is an input, sensing the state of P1. The 100k pullup sets P1-2 to high if P1 is open.

ESP off:
D3 is high due to internal 10k pullup, transistor is open.
D0 and the 100k pullup keep P1-2 HIGH, unless P1 is closed or D0 is LOW. Both will quickly discharge the P1-2 circuit. I tested that 1k is fast enough to still cause a pulse, P1 is instant anyway. Also, problems here would cause the oposite of my problem. This should send a pulse through C1, resetting the unit. After the pulse it SHOULD go to HIGH again, due to the pullup at RST, however, it does not. Instead, it stays low. It DOES go immediately HIGH again, as soon as P1-2 is HIGH, though, so the pullup seems fine. It basically acts like C1 was DC-conducting, however, I measured it not to be (as written above, got the right capacity and infinite resistance).

I think the reason why your output at P1 is always low(ish) is because you are implementing a voltage divider if D0 is GND. See? Try bypassing the 1K resistor. After all, I don't think it is necessary for your circuit.

Also, why are you using smd for debugging? It's a good idea to breadboard first, validate your design, and then use smd components.

Sorry, but you are clearly not reading what I am writing.

  1. I wrote multiple times that I had prior breadboard tests. That is e.g. why I know that I need more than 100nF.
  2. P1 is not the problem. That is an input. If I input 0V there, I expect a LOW pulse at RST, but I get a constant low. All of the rest of the circuit is pulled to HIGH, so that is basically the only place where 0V can show up (the only other place is over the meter, which I can observe when I measure the emitter, which slowly discharges over the meter until 3.3V-(transistor drop))
  3. The 1k resistor IS necessary. During sleep, D0 will be an output, and it will be normally HIGH. If I left the 1k resistor out, shorting P1 would cause an unprotected shortcircuit to ground, frying my unit. The minimal value to prevent this is 275Ohm. A too high value would discharge P1-2 too slowly, which diminishes the pulse behind C1. That is not at all my problem, again.
  4. If P1 is shorted, there is no notable voltage devider, because the restance to GND is ideally 0.
    The only situation, where a voltage divider comes in is during a timer wakeup. Then D0 is LOW, and will be connected to P1-2 over a 1k/100k voltage divider to 3.3V, leading to an effective voltage of 0.03V, which is fine as a ground signal.

ElCaron:
Sorry, but you are clearly not reading what I am writing.

  1. I wrote multiple times that I had prior breadboard tests. That is e.g. why I know that I need more than 100nF.

Actually, you mentioned it once, in passing.

ElCaron:
2. P1 is not the problem. That is an input. If I input 0V there, I expect a LOW pulse at RST, but I get a constant low. All of the rest of the circuit is pulled to HIGH, so that is basically the only place where 0V can show up (the only other place is over the meter, which I can observe when I measure the emitter, which slowly discharges over the meter until 3.3V-(transistor drop))

The thing is that the emitter voltage is not discharged over anything. Current only flows one way through a BJT and the direction of the arrow at the emitter shows you which way the current flows. Unfortunately, the emitter is connected to a cap, which is open circuit in DC. Therefore, the emitter voltage can’t discharge through a capacitor.

ElCaron:
3. The 1k resistor IS necessary. During sleep, D0 will be an output, and it will be normally HIGH. If I left the 1k resistor out, shorting P1 would cause an unprotected shortcircuit to ground, frying my unit.

No, you would still have a 100k between 3v3 and GND. I can’t think of anytime the junction of the two resistors and cap would be 3v3 when P1 is pulled low (thus short circuiting). It won’t happen.

ElCaron:
The minimal value to prevent this is 275Ohm. A too high value would discharge P1-2 too slowly, which diminishes the pulse behind C1. That is not at all my problem, again.

Why do you think you need to discharge P1?

ElCaron:
4. If P1 is shorted, there is no notable voltage devider, because the restance to GND is ideally 0.

Agreed.

ElCaron:
The only situation, where a voltage divider comes in is during a timer wakeup. Then D0 is LOW, and will be connected to P1-2 over a 1k/100k voltage divider to 3.3V, leading to an effective voltage of 0.03V, which is fine as a ground signal.

Is D0 an input to the circuit or an output of the circuit? Either way, the above explanation doesn’t make much sense.

Anyway, I did an LTSpice simulation to try and show you how I understand your circuit (your explanations are not very clear). I did a simulation of the circuit with P1-2 as a pulsetrain to simulate times when P1-2 is high vs low. I then plotted the emitter voltage and RST voltage vs time. Attached is the photo of the circuit and simulation. Looks like your circuit shouldn’t have worked in the first place (unless I’m missing something).

Honestly, I think you should redesign your circuit.

Also, FETs are better with logic, while BJTs are better with signal amplification.

Thanks for looking into this again.

Power_Broker:
The thing is that the emitter voltage is not discharged over anything. Current only flows one way through a BJT and the direction of the arrow at the emitter shows you which way the current flows. Unfortunately, the emitter is connected to a cap, which is open circuit in DC. Therefore, the emitter voltage can't discharge through a capacitor.

Yes, by now I also did an LTSpice simulation and found out the same. I really had a misconception about how the transistor and the cap would interact. So I build a particle accelerator :slight_smile:
I the linked thread, I have also proposed a solution (adding a Schottky to 3.3V at the emitter), after which the simulation give good results.

Power_Broker:
No, you would still have a 100k between 3v3 and GND. I can't think of anytime the junction of the two resistors and cap would be 3v3 when P1 is pulled low (thus short circuiting). It won't happen.

Imagine the 1k wasn't there, the contacts of P1 where bridged, and D0 is output HIGH (which is always the case when the ESP sleeps and the external trigger is closed). Then D0 at output high is directly connected to GND over P1, frying it.

Power_Broker:
Why do you think you need to discharge P1?

Because that is exactly what happens when I connect P1-1 and P1-2 OR D0 goes to output LOW. This discharges (pulls to GND) the net at P1-2, and is supposed to create a pulse behind the cap.

Is D0 an input to the circuit or an output of the circuit? Either way, the above explanation doesn't make much sense.

Both.
When the ESP sleeps, it is the output of the wakeup timer. It will normaly be HIGH, and sends a LOW pulse to reset (=wake up) the unit.
When the ESP is awake, it will be configured as an input to monitor the external trigger from P1.

One issue in your simulation, BTW, is that you put D0 on GND. That is usually not the case, only during the wakeup time pulse. Else it will be either HIGH or a high impedance input (see below).
I might look into changing over to a FET, though.

Ok, I put in a FET. Or two: Left FET simulates P1’s GND or nc, right replaces the BJT. Why did my pulses in the RST net so short, now?
rst_simu3.png

BTW: I am already in the redesign mode. Somehow I fucked up the PCB - the PCB layout did not match the most recent version of the schematic, for some reason …

reset…

if your circuit doesn’t match the pcb we’re all at sea.

straighten it all out and talk to us again.

Allan

As far as I can reconstruct, this is the actual circuit on the PCB:

rst1.png

The only thing that cannot be easily followed in the closeup is the one trace from R4 to RST, as it is somewhat hidden unter the R4/RST label.

I am not sure how this happend, it is nothing that I remember as an intermediate version of the circuit. Probably, I wasn’t as rigorous as I should have been when imported a new netlist, since deleting orphaned footprints also deleted my perfboard pads (I didn’t put them into the schematic …). Still no idea how that got through the DRC test.

In any case, the actual circuit still does not explain to me, how the situation in the zoomed out image can happen. Without looking at any schematic, D0 is clearly separated from RST be the cap, as seen in the closeup, and RST has a pullup, as seen in the zoomed out image. Still, the oscilloscope in the picture shows a static 0.64V. at RST.
The part that is actually fucked up, P5, isn’t even used. And while this circuit does have the problem with the floating cap, this should lead to a constantly high RST, not to one that almost follows D0.

Anyway, that circuit is lost, since the external trigger pins ended up on the wrong side of the cap. I can still use it for projects using the wakeup timer, but the external trigger is gone. No need to spend more time on this for anyone who isn’t fond of following traces on pcb pictures just for the sake of finding out what’s going on …

What I am more interested in now is if I should replace the BJT with a MOSFET, and if yes, why the spikes on the RST net are so much shorter than the ones before the FET in the simulation in post #13. This was not the case with a BJT, nothing else changed.
If there is an easy answer and solution to this issue, I would also appreciate suggestions for an SOT-23 or similar logic level MOSFET for this purpose.

I'm looking for a similar solution and found the below, could be helpfull: