I want to set the PWM frequency to 500khz to control the motor.
What should I do?
It doesn't have to be exactly 500khz.
I want to set the PWM frequency to 500khz to control the motor.
What should I do?
It doesn't have to be exactly 500khz.
Your post was MOVED to its current location as it is more suitable.
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Read TC1 (Timer/Counter 1) data sheets of ATmega328P Microcontroller. You will be known that TC1 hardware could be used to generate exactly 500 kHz PWM signal. Try to write some codes based on your reading/understanding of the data sheets; post those codes and someone in this Forum may help you.
Why 500kHz? The controller is RC compatible so that you can (and should) use the Servo library at the RC standard timing with pulses of 1 to 2 ms duration.
Easy. Just set the timer of your choice to 500 kHz by setting TOP to 16 MHz / 500 kHz -1. That's 31. Then you can set the Output Compare Register to a value from 0 to 31 giving you 32 levels of PWM.
You will need a Waveform Generation Mode that is FastPWM and allows you to set TOP. For 8-bit timers that will be WGM 7 and for 16-bit timers that will be WGM 14 or 15. Note: Since WGM 7 (8-bit) and WGM 15 (16-bit) use OCRnA to hold the value of TOP, the 'A' channel can't be used as a PWM output.
1. A PWM signal has a frequency (fpwm) and ON-period (the duty cycle).
2. Timer/Counter 1 (TC1) of ATmega328P MCU of the UNO Board supports the generation of PWM signal of Step-1 into two channels -- Ch-A at DPin-9 and Ch-B at DPin-10 of the UNO Board (Fig-1).
3. The relation among fpwm (500 kHz), clkSYS (16 MHz), N (TC1 Clock Prescaler), and OCR1A (fpwm determining register in Mode-15, Fig-2) is:
fpwm = clkSYS/(2*N*OCR1A)
N = division factor for TC1 prescaler = 1
clkSYS = 16000000 Hz
OCR1A = clckSYS/(2*N*500*10E3)
OCR1A = 16000000/(2*1*500*10E3)
OCR1A = 16
4. In Mode-15, the OCR1A register controls the frequency of the PWM signal. Therefore, TC1 will not be able to produce any PWM signal on Ch-A (DPin-9). Now, the 500 kHz PWM signal will be available at Ch-B (DPin-10). The duty cycle will be controlled by the content of OCR1B register.
5. The Sketch (untested)
void setup()
{
Serial.begin(9600);
pinMode(10, OUTPUT); //DPin-10 will deliver PWM signal for Ch-B
TCCR1A = 0b11100011; //COM1A1 COM1A0 COM1B1 COM1B0 b4 b3 b2 WGM11 WGM10; Mode-15 PWM; inverting
TCCR1B = 0b00011001; //b7 b6 b5 WGM13 WGM12 CS12 CS11 CS10; Mode-15 PWM; division factor = 1; clkTC1 = clkSYS/1
OCR1A = 16; //fpwm = 500 kHz
TCNT1 = 0x0000; //initial count
}
void loop()
{
if (bitRead(TIFR1, OCF1A) == HIGH)//if TCNT1 matches with OCR1A;change duty cycle
{
bitSet(TIFR1, OCF1A); //clear flag
OCR1B = map(analogRead(A0), 0, 1023, 0, 13);//new value for new duty cycle
delay(2000); //test interval
}
}
That '2' factor is for Phase Correct PWM and CTC but not for Fast PWM. The OCR1A register is used for some but not all PWM modes. The datasheet calls that value 'TOP'.
You forgot the -1 factor. TOP will be 15 for Phase Correct PWM and CTC or 31 for Fast PWM.
You are setting COM1A0 which will give you inverted PWM on pin OC1A. But you are using WGM15 which uses OCR1A for TOP so you can't use OCR1A for PWM. I'd set COM1A0 and COM1A1 to zero.
You are using WGM15 which is a Fast PWM mode so you need 31 instead of 16 to get 500 kHz.
You don't want to use the full PWM range (0-31)?
You are right. The Fast PWM works on single-slope mode and hence the equation for fpwm is:
fpwm = clckSYS/(N*(1+TOP))
==> fpwm = clkSYS/(N*(1+OCR1A))
==> OCR1A = (clkSYS/fpwm) - 1 //N = 1
==> OCR1A = (16000000/500000) -1
==> OCR1A = 31
TCCR1A = 0b00100011; //COM1A1 COM1A0 COM1B1 COM1B0 b4 b3 b2 WGM11 WGM10; Mode-15 PWM; inverting
Should it not be less than 31 and greater than 0 ( 1 - 30) in order to see a real PWM signal (not 100% OFF and not 100% ON)? (Fig-1)
Figure-1:
1. When you say about 32 levels of PWM signal - does it mean the following?
The duty cycle of the 500 kHz PWM signal can be incremented in 32 steps (starting from 0); where, each step is (1/500000)/32 = 0.0625 us.
2. In Mode-14, TC1 can generate PWM signal at both Ch-A and Ch-B of identical frequency being controlled by ICR register. The duty cycles could be different as they are are controlled by OCR1A and OCR1B registers respectively. Correct?
Yes.
Yes.
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