You could put the ROM monitor and any drivers up there as well. Maybe a jump table of some sort.
I like to start RAM a $0000 and put the stack at the top of that. I suppose it might make some sense to start paged memory at $0000 and put fixed above that. Memory mapped peripherals below ROM area.
Looks like you’re having fun thinking about it. I’m about to let my mind rest on a bike ride.
Here is a start. This uses 16k RAM swap pages, location zero. The nor gates select either the current processor high address bits, or the page bits stored in the 373 latch. Then there is partial address decoding, producing peripheral selects and a high memory write protect signal for addresses E000-FFFF.
I didn't finish it down to the device select inputs, leaving that for last.
Well, the fixed memory area in that design is between 0x4000 and 0xDFFF, and the 6809 S stack grows down, so the stack should start near or at 0xDFFF I guess. Going up from there in memory, peripherals follow at 0xE000, the 8 available chip selects from the 74HC138 decoder (the logic that "knocks a hole" in the RAM space for that isn't shown or complete yet). The RAM that follows it, from 0xE100 to 0xFFFF is write protected. The block from 0x0000 to 0x3FFF is the paged swap area.
A simple summary for the casual reader - the first 1/4 of the 64k memory can be mapped to any 16k segment of the 512k SRAM, which is also battery backed up. There is a bit more than 32k fixed RAM, then a small memory mapped peripheral space, and after that, about 8k of write protected SRAM which serves the role of ROM.
No, there are a lot of support IC's that were pretty rare, special order even back then. I think now, almost unobtainable. Some of those rare chips are available, but in the range of $100 each.
With the 512k RAM, I thought a 6829 MMU would be perfect. But that chip is one of the rare ones.
I did think of bringing out the full bus on an expansion connector, so you could connect some IC's like that as an add on. Like the Apple II.
I still need add address decoding and some buffering to the schematic but this is the basic project. I'm still learning the finer points of Kicad so this preliminary schematic is pretty rough.
It's a good idea to add the buffering with so many parts on the bus. I have fewer, so I'm not thinking about adding that yet. Everything there looks good on the face of it. All I've really done, is clean things up and add one gate to start building the memory disable for peripheral access circuit (just below the 138):
Where I placed LS parts, it's just because there wasn't an HC analogue in the KiCad parts database. In reality, everything will be HC or similar high speed CMOS.
I'm not so sure now about an expansion connector. Really, I think I many only want it for the one-time bootloader installation.
Just more cleanup here, some component changes. The DS1315 is looking like it might have a dwindling supply, so that's out. The DS1210 (MXD1210) looks to be in normal supply so I ordered those. The remaining options for parallel interface RTC are not good, so I plan on adding the I2C expander and DS3231.
I made the same choices. The DIP version of the PCA9564 seems to be obsolete so I've ordered a Schmartboard DIP adapter for the TSSOP part I have in hand. I'm just mulling over the ratio of program storage to RAM ratio I want now. I am leaning toward a mini ROM monitor in EEPROM and maybe 256 bytes of I/O and the rest NVRAM via the DS1210.
A future goal is to get FLEX running. That will require figuring out how to get the disk images loaded. An OG 8" floppy would be cool but an SD card equivalent will probably be the practical solution. Studying now how difficult SPI will be.
I dragged out my vintage MC14411 baud rate generator chip yesterday and fired it up. Still works fine!
New thought! Compact Flash has a parallel interface.
Me too. I saw it coming and ordered a pile of TSOP to PDIP adapters. If you don't want paged memory I suggest two 62256's to round out 64k. At least, that is what I would do. That is still a viable option for my 6803 system, which will be extremely stripped down, maybe only 32k. Last time I looked for an EEPROM programmer, it seemed hard to find an inexpensive one. Hence my reticence about using PROM.
The ELF II uses CF memory cards for disk storage. The neat thing about those, the cards have a built in IDE disk controller. The interface is a parallel bus, I am still catching up so haven't looked at that yet. So it's really easy to add to an 8 bit system.
I downloaded the missing parts footprints for KiCad. The challenge now is to figure out how to install them.
Would FLEX fit in a little bit less than 512k? (answers own question, I guess not...)