The first line is this:
:10000000082C0020B9280000B5280000B528000001
The first 4 data bytes in reverse order are 20002C08, which is an address within the 32k RAM of SAM D21 (20000000 to 20007FFF). That sure looks like the initial stack pointer, which ARM puts in the first 4 bytes. The 2 lowest bits are cleared, as required for 32 bit alignment of the stack.
The next 4 bytes in reverse order are 000028B9, which looks like a thumb state program address (notice the LSB is set), also will within SAM D21's flash address space (00000000 to 0003FFFF). On ARM processors, there's 2 instruction modes. Cortex-M chips only support thumb mode, so address words always have their LSB set. If the LSB is clear, it causes a hard fault because the chip doesn't support the other mode.
The next 8 bytes are similar-looking addresses (with LSB set), which would be the ARM NMI and Fault exceptions. Then there's a string of zeros, which correspond nicely to the ARM exceptions that aren't implemented on Cortex-M0+, followed by a lot more groups of 32 bits that look like program addresses for the Systick exception and NVIC interrupt vectors.
I'm pretty sure this data is code meant to run on a Cortex-M0+, not an AVR32.