Figure 10 is a bit of a mystery to me… I have looked at it multiple times, upside down and back to front and it doesnt float my boat. But i think we are on the same page with as soon as you assert that chip select, you are going to read what ever is coming back to the micro from the last device and it will be either a status or a “echo” dependent on what was sent to it last.
As for reset, im glad someone else can clairfy this too. Yes, no reset pin, so hard reset can only be done via full power down, or perhaps some state transitions internally but im yet to understand the internal states.
I agree, its hard to define my current understanding of the “Echo” as it would contradict the datasheet. But If I can hold the chip select line low and see the exact control word I pumped in then I know that it made it to the SPI device. So if it has chosen to echo something different to me, then it means something larger is at play. A line in the documentation that keeps resonating with me but is not clear is “If CSN is negated, SO pin is in tri state condition and the fault register is reloaded (latched) with current filtered status bits.”
I really appreciate being able to bounce this of someone else. So keep up the great work!
Hahahah!
