Line 2 has short pulses that signal when data is ready. It sits normally high and data is valid on the rising edge of the pulse.
I must design a digital circuit that outputs a high level whenever the data sampled at time t differs from data sampled at time t-1. It should also be high at startup (i.e.: when there is no t-1), but this is not too important.
I can only use basic 7400 ICs: AND/OR/NAND/NOR gates and 7474 flip-flops.
SukkoPera:
I must design a digital circuit that outputs a high level whenever the data sampled at time t differs from data sampled at time t-1.
I can only use basic 7400 ICs: AND/OR/NAND/NOR gates and 7474 flip-flops.
Sounds like an XOR function will be required. You can build one with the parts you've listed.
Right, I've been thinking about it in the meantime: the idea is to make a 2-bit shift register with a 7474. The shift register will be fed with the current data bit, and the previous one will be shifted in the 2nd position.
Both bits will then be supplied to a XOR gate (I'll see later whether to build that up with other gates or use a 7486) and that will be my output.
I can make sure that the initial state is high through two RC networks on the set/reset pins of the flip-flops.
There's a complication, but I'll introduce that later. Will things work like this so far?
Thanks a lot. This part is rather clear, on with the complication: The output of this circuit must trigger a NE555 configured in monostable mode whenever a change is detected.
This, means that I have to generate a negative pulse. The circuit I proposed works mostly fine for this (except that the output needs to be inverted), with a single exception as far as I can see: if the signal changes at every clock cycle, the XOR output will stay high (low if inverted), while I need it to trigger the 555 every time.
It is a XY problem. And it sounds as a homework. If it truly is you should be honest and admit it. In either case you should tell us what you want to achieve and what you may use for it (and what limits you in using other things).
SukkoPera:
The output of this circuit must trigger a NE555
Assuming the NE555 output pulse is shorter than the period between clocks then...
Your input clock, which clocks bits into your 2-bit shift register, could clock a third 7474 flipflop.
With D permanently high it would give you an output which goes high on clock which you could combine with the other signal to trigger the NE555
Then you have to figure out how to clear that 3rd FlipFlop ready for the next input clock.
@Smajdalf: A homework? Oh, come on . I have >4000 posts and you think I am secretly asking for help for a homework? Not really. This is meant to be an adapter to use PC floppy drives on old Amiga computers. The main issue is the generation of a /READY signal, which PC drives lack. The conditions for it to be active are all trivial except the one I'm tackling, that is that the drive should not be ready for ~18 ms whenever the head step direction is reversed. There are several such adapters around, but they are all missing this bit. The direction signal is what I referred to as "data", and the step pulse is my "clock" signal. I want to use only common chips as I will publish the design and I would like everyone to be able to buy the PCB and build the adapter on their own without going crazy for sourcing parts. The only reason I didn't say this to begin is with is that it was way more verbose, as I guess you can see for yourself now. I need help even with ~4000 posts because I'm better at writing software than at designing circuits.
@TonyWilk: What if I just use another 555 (or the second circuit of a 556 at this point) instead of the flip flop to generate a pulse as short as I need and then I AND that with the XOR output? That way it will be cleared "automatically".
SukkoPera:
What if I just use another 555 (or the second circuit of a 556 at this point) instead of the flip flop to generate a pulse as short as I need and then I combine that properly (still need to figure out how) with the XOR output? That way it will be cleared "automatically".
I was thinking of: 2bits -> XOR -> NAND with 3rd D-Type = LOW to trigger 555. Invert the 555 output (use a spare NAND) to CLEAR the 3rd D-Type.
What I'd worry about is any 'race' condition where you get bits of spikey output from the XOR as the D-Types change state...
Maybe the 2nd 1/2 of a 556 might be a good idea, if this will trigger from the same clock that is clocking the bits then I reckon 74HC74 and 74HC86 will have switched by the time a 556 drives the output.
So... 1/2 of 556 set as short output pulse, triggered by clock.
Same 2 x D-types and XOR gate as before
NAND the outputs of those two to get a LOW for the other 1/2 of the 556
Can't think of any way to do the logic with less than two packages (e.g. 74HC00,74HC86)
I admit I don't really understand all the floppy disk stuff. But I think you should be able to NAND output from the XOR gate with clock signal? So you get trigger pulse for duration of clock signal but only if the XOR is high.
EDIT: I think using open drain (N)AND gate and wired-OR you may do it with one package? XOR = \A.B + \B.A
Smajdalf:
I admit I don't really understand all the floppy disk stuff. But I think you should be able to NAND output from the XOR gate with clock signal? So you get trigger pulse for duration of clock signal but only if the XOR is high.
Ah, that could be a 'race condition' thing I was worried about...
If the XOR is currently HIGH, but will go LOW on the next clock:
If you NAND the clock with the XOR you will get a short spike while XOR is high
then the signal makes it thru the D-Type flipflop and the XOR gate goes LOW and the NAND output switches again.
With 74HC logic, the approx. time for a FlipFlop (20nS) + time for an XOR (15nS) = 30nS
so you could get a 30nS spike out of the NAND when you don't expect it.
555 timers are really slow, so it would be 100nS or so before its output switched.
you'll have to check if the clock you are using is wide enough to trigger one tho.
It's really handy to carefully draw out a timing diagram for this sort of thing, include all the propagation delays of gates and flipflops - drawing on graph paper makes it easier (see linked pdf) e.g.
Diagram:
. I have >4000 posts and you think I am secretly asking for help for a homework? Not really. This is meant to be an adapter to use PC floppy drives on old Amiga computers. The main issue is the generation of a /READY signal, which PC drives lack. The conditions for it to be active are all trivial except the one I'm tackling, that is that the drive should not be ready for ~18 ms whenever the head step direction is reversed. There are several such adapters around, but they are all missing this bit. The direction signal is what I referred to as "data", and the step pulse is my "clock" signal. I want to use only common chips as I will publish the design and I would like everyone to be able to buy the PCB and build the adapter on their own without going crazy for sourcing parts. The only reason I didn't say this to begin is with is that it was way more verbose, as I guess you can see for yourself now. I need help even with ~4000 posts because I'm better at writing software than at designing circuits.