I am working on a low-power weighing scale project using an STM32L031K6 microcontroller, an HX711 24-bit ADC, and a RAK3172 (LoRaWAN) module.
In my firmware, I use a moving average filter. To eliminate RF interference, the software strictly waits for the measurement cycle to finish before triggering any LoRa transmission (no simultaneous read and transmit operations).
Current Setup & Hardware Details:
MCU: STM32L031K6
ADC: HX711 (AGND is directly tied to system GND, shared with the MCU)
RATE Pin: Hardwired to GND (10 Hz sampling rate mode)
AVDD Decoupling: 100 nF and 10 µF capacitors are placed on AVDD
. - Load Cell Cable: Directly soldered to the PCB without an unbraided shield/drain wire.
Problem: When a static weight is placed on the load cell, I am observing a jitter of around 100 mg to 200 mg. I would like to reduce this noise floor even further for higher precision.
My Questions: 1. Given that RATE is at 10 Hz and AVDD is decoupled, what other PCB layout or hardware modifications could improve the signal-to-noise ratio (SNR) on the HX711? (e.g., analog ground plane separation, ferrite beads, LC filtering on AVDD).
2. Could directly soldering the unshielded load cell wires to the PCB be the primary source of this ~100 mg noise?
3. Since the HX711 seems to be reaching its physical ENOB limits here, would upgrading to an industrial 24-bit ADC like the TI ADS1231 or ADS1232 yield significantly better stability?
4. What software filtering techniques (e.g., Exponential Moving Average, Median Filter, Kalman) do you recommend pairing with low-sample-rate weigh scales?
I have attached my schematic for reference. Any feedback or hardware recommendations would be greatly appreciated! Thanks!
My HX711 library implements different filters. So it is relative easy to test which gives results best matching your requirements.
Personally I like a median filter as it eliminates outliers (depending on nr samples)
What is the range of your load cell? Depending on the range the noise might be unavoidable. In my experience from the 24 bit theoretical resolution 16 at most 20 bits are stable.
That is correct. The datasheet does not give information on noise performance but as @robtillaart points out the effective number of bits can be as low as 16.
Thanks for the insights! My load cell is 5 kg, so 100–200 mg jitter gives ~25k–50k stable counts, perfectly matching the ~16–17 ENOB limit of the HX711. I am already running a 2-stage DSP pipeline: 1. Trimmed Mean: 15 samples, drop top 3 & bottom 3 outliers, average middle 9. 2. EWMA: Applied to the trimmed mean for smoothing. Even with this DSP setup, 10 Hz rate mode, AVDD decoupling, and LoRa isolated from ADC reads, the jitter stays at 100 mg. I’ve clearly hit the HX711's noise floor. To reach 5–10 mg stability, I am considering upgrading to the TI ADS1232. Question: Before spinning a custom PCB, can I reliably test the ADS1232 on a breadboard/perfboard with jumper wires, or will stray noise from loose wiring prevent me from seeing 5–10 mg stability? Is a custom PCB with a ground plane strictly required even for initial testing?
A jitter of 100–200 mg is not unusual with the HX711, especially when using a 10 Hz sampling rate. Before replacing the ADC, I'd focus on the analog layout. Keep the load cell traces as short as possible, use a solid analog ground with careful routing, avoid high-current digital return paths near the HX711, and ensure the excitation voltage is clean. Additional filtering on the supply can help, but layout and grounding typically have a greater impact.
Directly soldering the load cell wires isn't necessarily the main cause of the noise, but long unshielded cables can pick up EMI. If the cable is more than a short distance, using a shielded twisted-pair load cell cable with the shield connected to ground at one end is usually beneficial. On the software side, a median filter followed by an exponential moving average (EMA) often provides better stability than a simple moving average while remaining responsive. Upgrading to an ADS1231/ADS1232 may offer some improvement, but unless the analog front end, power supply, and PCB layout are already well optimized, the gains may be modest.
Thanks for the solid feedback! You're totally right about the layout and grounding impact.
Currently, I do NOT have a split between AGND and GND—they share a unified ground plane on my PCB, which might be letting digital return currents contaminate the analog readings.
I've attached my current PCB layout around the HX711, AVDD, and GND trace routing.
Could you take a look and suggest how I should properly separate AGND/GND and optimize the ground return paths to minimize this noise? I’d really appreciate your layout recommendations before considering an ADC upgrade!
Since you're evaluating the stability of a nearly static measurement, a histogram may also be useful. It shows the complete distribution of the readings and makes it much easier to compare the effects of different filters or hardware changes than looking at a single jitter value. I recently wrote an article including an Arduino implementation of an auto-centered cumulative text histogram: Auto-Centered Cumulative Text Histogram
Without going to extremes with layout, shielding, filters, etc., I think you are at the limit that can be done with the HX711 and most of the inexpensive 24 bit bridge circuits.
You might have a look at the Analog devices AD7190.
