I’m making a PCB for my thesis. The PCB includes the FT232H chip connected to USB-B port on the right side. On the left side i got the SX1276 breakout board, which does SPI communication to the FT232H. I would appreciate some feedback and suggestions from you. Thank you
Which software you are using for Schematic Capture and Layout?
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Power traces from usb connector should be thicker.
Crystal is “too far” from its pins.
Some bypass caps seem to be positioned oddly.
Some traces branch weirdly.
Those are BIG diodes (for protection?) on the usb data lines. Are they right? Are they needed?
More later.
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Does the board circuit work, it looks like your designing a LoRa module as a USB connected device, for a PC perhaps ?
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As mentioned, traces could be wider.
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GND pour cross-unders could have 0R SMD resistors across the middle of the traces.
Or, use 0R SMD resistors on the component side instead of cross-unders on the GND pour side. -
Are you wanting mounting holes ?
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Add an option for having a Ferrite bead on the GND of the J1 USB-B line for common mode noise.
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Having indicator LEDs is always nice, they can be enabled with jumpers if necessary.
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Can the FT232 VCCD actually supply enough current for the SX1276?
can you elaborate on the positions of the bypass caps as well as the traces branch.
The diodes are TVS diodes, but i figured out i got the footprints wrong.
it's not just the SX1276 alone. It's the SX1276 breakout board which i got from a manufacturer. According to them, the current consumption is 12mA during receiving. So i would say the FT232H VCCD (VCCIO) can supply enough current.
In other cases, if there's not enough, can you please tell me what i should do? implementing a voltage regulator that takes input voltage from VBUS ?
So this is a receive only LoRa device ?
the key of my thesis is to implement USB interface and analyze using a USB sniffer (Openvizsla).
I only need the communication from PC to FT232H to a chip - the Lora chip (so i only need one of the Lora chip function - receiving). So i would say yes
I used the export function from Kicad for capturing the schematic. For the layout, i simply screenshot it
you're right
You have the multiple bypass caps for each supply located right next to each other. Instead, you should have one next to each IC supply pin. Sort-of like this:
(yes, this can make breaking out the signals near the power pins painful.)
Traces: I had in mind the 4 separate traces going into the power pin of the EEPROM, the USB data signal going around the back to the protection diode, and the traces to the crystal.
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If you believe that is true then OK but I could not find any specification for maximun current draw on VCCD but the typical is only 54mA
I would make sure before you go any further.
In LoRa mode the SX1276 can draw 13.8mA
I think you should spend some reading and understanding the datasheets of the ICs you are using. You need to have the schematics correct before you can do a layout.
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I'd do that, yes. Don't rely on the flimsy internal regulator of a USB-UART interface.
There's some quirkiness in the schematic, such as two different labels for effectively the same power net (V3V3 & VCCIO turn out to be one and the same). Some other nets are also drawn in a counter-intuitive way which makes it harder than necessary to follow your schematic; e.g. the work around the DO/DI pins of the EEPROM, placement of C2 & C3 etc.
IDK if the bypass caps on the crystal are correctly dimensioned; I assume you've verified this. They seem slightly on the large side to me.
R2 & R3 are kind of superfluous unless you're mounting those because you may want to change them to something like 22R or 47R later on. Not sure what you have in mind with them. R1 is equally puzzling.
I've not checked whether you've correctly connected everything around the FT232, esp. pins like TEST, REF, but also nRESET (does it require a pullup resistor or is it OK to pull it up without one? IDK - verify with the datasheet) etc.
Overall the board can be shrunk by about 60% in size.
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The junction capacitance (3000pF) of the TVS diodes is way to big for USB2 bus speeds and possibly for full speed mode as well.
I think you need to spend some reading and understanding the datasheets of all the parts ans ICs used in your design. You need to get the schematic correct first before you start worrying about layout.
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What is the current consumption when transmitting?
Lora involves each end of the comms link Transmitting and Receiving to ensure valid packet transmission.
Tom... 
The routing of tracks is not good in many places, and just bad near U4 chip - the tracks are overlap with neighboring pads.
Did you run a Kikad EC check tool?
Thank you everyone for the feedbacks. I will work more on the schematic to make sure everything is correct, before moving to the layout
I should perhaps add WRT Bypass caps that they're frequently drawn next to each other and "out-of-the-way" on schematics (like your C4, C5, C6) so that they don't clutter the logic of the actual signal paths, but that is NOT supposed to be the way they end up laid out on the PCB.
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