I'm working with an ATtiny85. At minimum it seems it should have a 0.1uF cap near the power pin, but does it need to have the reset pin pulled high?
The reason I'm questioning this is because it looks like the Digispark Kickstarter board I have doesn't have the reset pin connected to anything. Digispark Kickstarter schematic
I'm planning to use just the ATtiny85 chip. Would I need an external pull-up resistor to pull the reset pin high? Would it be an option to use the internal pull-up resistor, or could I maybe use the adjacent pin to pull the reset pin high? (I'm not planning to use the two pins near the reset pin.)
On the Uno R3 schematic, I see both a 10k pull-up resistor and a diode in parallel. What is the diode for? Uno R3 schematic
The Digispark does not have a reset pin. Reset has been disabled on the ATtiny85 through a fuse setting. PB5 is a regular I/O pin on Digispark.
Another design which uses the ATtiny85 and is almost identical to the Digispark is the Adafruit Trinket. Adafruit Trinket does not have disabled reset, so it has one less data pin. They do not use a pull up resistor on the reset pin. I advise read the ATtiny85 data sheet to find out under what circumstances a pull up resistor is recommended.
On the Uno, the diode on the reset pin limits the voltage going to the reset pin to 5V, so it won't spike higher when the DTR signal from the USB-to-serial chip goes from low to high. Older board designs do not have it, and it is not absolutely essential (my opinion), just a good idea.
Thanks for the info. Now that you mentioned it, it makes sense that the Digispark is not connected during programming until after the compiler prompts for it since reset is disabled.
I plan to program raw ATtiny85's using an Arduino board, then transfer them to their new homes. I need to check on how reset is used in that case.
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
But I wonder how often it really matters.
How much extra current are we talking about?
[quote author=Coding Badly link=msg=2573558 date=1453263296]
I suspect @Paul__B was asking why do you believe this is true...[/quote]
It's on Nick Gammon's website, here.
But I just tried to duplicate his result and I don't see what he measured. The current I'm reading is the same in power down mode whether or not the internal pull-ups are enabled.
jboyton:
I'm not sure. I would guess that it's because in sleep mode inputs are clamped to ground.
That would be totally absurd and is clearly not the case!
atmel:
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 79 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 236 and ”DIDR0 – Digital Input Disable Register 0” on page 251 for details.
But I just tried to duplicate his result and I don't see what he measured. The current I'm reading is the same in power down mode whether or not the internal pull-ups are enabled.
No, there simply is no reason why enabling the pull-up would draw more current. It is itself, just a P-channel FET which draws no gate current and can draw no current if its drain is not connected to anything else.
It does. But the pin is disconnected from the outside world, including the pull-up resistor, when SLEEP disables the pin. (That's the purpose of that weird boxy symbol.)
