Hey,
What would happen if i would connect a digital IO pin to reset and pull it low?
Will the uC ruin itself or reset?
Ruin? No.
But the result might be unpredictable. On-RESET, all I/O pins go to a high impedance state. After that occurs, who knows what that signal will do at that point.
This has come up before, I believe the thinking is that reset may not be held low long enough to cause a valid reset.
If reset is pulled high, it will high as soon as the IO pins go inactive.
From Section 11 of the '328 datasheet:
"An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see ”System and Reset Characteristics” on page 324) will generate a
reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the
delay counter starts the MCU after the Time-out period – tTOUT – has expired. The External Reset
can be disabled by the RSTDISBL fuse, see Table 28-7 on page 299."
"Minimum pulse width on RESET Pin ... 2.5uS Max"
You need some external hardware to self reset, a one-shot timer or something similar.
Rob
Graynomad:
You need some external hardware to self reset, a one-shot timer or something similar.
Rob
It can also be done with just software using the watchdog reset.
--- bill