Net/pin names with a line (bar) above means that the signal is active low, you often see this in data sheets and on schematics inside the chip boundary, however IMO it's bad practice to use the bar for a net name. Why? Because if you have another net directly above it the bar can get lost in the line for the other net. Also that over-bar is almost impossible to show in documentation.
For this reason it's common for an active-low signal to have a normal printable character either before or after. eg
My preference of the the # but whatever.
Also an active low pin on a chip usually has a dot on the edge of the chip rectangle.
lines that ended in arrows or other shape must be joined with the others that ends with the same shape?
No, I don't think that's normal although there are a lot of practices around.
I always use the arrow for a signal when the net is not connected directly and it is the SOURCE of the signal, for example in your schem the VCC arrow on SV1 pins 1/2 is correct (according to my world). It is not correct everywhere else because they are not sources of the VCC signal, they should have a flat bar indicating that the signal comes form elsewhere.
Now I see that most schems here use the arrows as is shown in your example, so I may be the odd man out with this.
may be a logic pin it means that works with just a logic voltage 3.3v up to 7v,
No name will tell you the min or max voltage for that pin, you have to read that from the data sheet. VCC on one chip might be 2v5, on another 6v.
EDIT: RE using VCC, I used to do that all the time because there was usually no confusion, everything was 5v, these days I label the nets with the actual voltage or at least something that leaves no room for doubt, 3v3, 5v, 12v etc, not VCC because on a single board there might be 2-3 "VCC"s.