The clock signal that can be used in the FPGA to drive PLLs is that of pin E2?
The one called SAM_PORTS.GCLK?

If so, what frequency does it have? 48MHz?

Hi Riccardo,
Yes, we are deriving all clocks from pin E2 using a PLL. current bootloader is set to drive that pin at 48 MHz when you call FPGA.begin().
alternatively you can use the internal oscillator in the FPGA however that can't drive a PLL so it probably won't be of much use unless you need a clock which is present also if SAM is not clocking FPGA.

In the VidorUtils.h file I find it written:

		// Start clocking the FPGA; this function is declared weak and can be overridden
		// with a custom implementation (or can be left untouched if FPGA is clocked internally)

And indeed, shortly before, the enableFpgaClock() function is defined as follows:

__attribute__((weak)) void enableFpgaClock() {}

So, at the moment, there is no way to enable the clock? Or is it always enabled?

I answer myself, the function enableFpgaClock() is redefined in the variant.cpp file of the mkrvidor variant:

void enableFpgaClock() {
  // Will be called by the Vidor library begin()
  pinPeripheral(30, PIO_AC_CLK);
  clockout(0, 1);