I have a 3.3V device that I want to interface over SPI with a 5V Uno.
Will the following approach work okay?
Might do.
Why no pullup on CS?
CS has an internal pullup resistor.
Will the following approach work okay?
Depends on which device is the master and which the slave.
The Uno is the master and the device is the slave.
The device is rated for a clock up to 10 MHz. Would this method of level shifting reduce the maximum clock speed possible as compared to an IC based level shifter? Any other caveats with doing it this way?
The MOSI won't work (Master Out Slave In).
If your device has 5V "tolerant" I/O, things could be simplified. What is the device?
dlloyd:
The MOSI won't work (Master Out Slave In).
Can you explain why it won't work?
dlloyd:
If your device has 5V "tolerant" I/O, things could be simplified. What is the device?
Absolute maximum at one of the interface pins is supply volatage + 0.3V.
Can you explain why it won't work?
The MOSI signal originates at the UNO (SPI Master). The diode blocks the signal. Same thing for SCK and CS.
An interface suggestion (updated):
dlloyd:
The MOSI signal originates at the UNO (SPI Master). The diode blocks the signal. Same thing for SCK and CS.
Really? My understanding of electronics is very primitive, but I'm certain you're wrong about this.
The way I thought it worked was that when MOSI is at 5V the DI pin will be pulled up to 3.3; and when MOSI is at 0V the diode will allow current to flow, pulling DI down to 0.7V or whatever the diode voltage drop is.
dlloyd:
An interface suggestion:
Imgur: The magic of the Internet
Will that method impact maximum SPI clock speed?
Absolute maximum at one of the interface pins is supply volatage + 0.3V.
So that will be a no then.
Can you explain why it won't work?
The diode while dropping the voltage for a voltage HIGH, it will not allow the signal on the pin to go to a logic ZERO.
My understanding of electronics is very primitive, but I'm certain you're wrong about this.
I am certain your understanding of electronics is very primitive. And I am certain he is right.
Grumpy_Mike:
The diode while dropping the voltage for a voltage HIGH, it will not allow the signal on the pin to go to a logic ZERO.I am certain your understanding of electronics is very primitive. And I am certain he is right.
The data sheet says that the maximum value for logic zero is 0.2*VCC, which would be 0.66V at 3.3V supply. That's essentially the same as the diode voltage drop.
So would that mean it wouldn't work or just that it would be too close for comfort?
The data sheet says that the maximum value for logic zero is 0.2*VCC, which would be 0.66V at 3.3V supply. That's essentially the same as the diode voltage drop.
Yes but that is the forward voltage drop, When the output is a zero then the diode will be reverse biased so in effect the input will be floating.
Grumpy_Mike:
Yes but that is the forward voltage drop, When the output is a zero then the diode will be reverse biased so in effect the input will be floating.
As the diagram goes, when the MOSI of the UNO pulls LOW, the diode will be conducting and pull the 3.3V device DI LOW.
The way I thought it worked was that when MOSI is at 5V the DI pin will be pulled up to 3.3; and when MOSI is at 0V the diode will allow current to flow, pulling DI down to 0.7V or whatever the diode voltage drop is.
This is true. I see that you're using the diodes to convert the 3 outputs from the SPI master to "open drain". I guess it may work (boarder-line) at low speeds, but I still don't know what the device is and what the DC characteristics are. No matter.
If it works, the issue of slow rise time at the device will limit the speed, especially with only 10K pullup resistors. If you use lower resistance to get a stronger signal, then the voltage drop across the diode may increase to say 0.8V, and the VOL at the UNO might be around 0.4V, so will a VIL of 1.2V at the device be low enough?
I haven't used an UNO, but I don't think its possible to set the SCK frequency to 10MHz ... 8 MHz would be the closest match to the device's max SCK frequency of 10 MHz.
10 MHz is the device clock maximum. The maximum SPI clock frequency on the Uno is half the oscillator freq. So yes, it's 8 MHz.
The device is the Bosch BMP280.
Clock speed isn't a high priority since it is milliseconds or even tens of milliseconds between small packets of data.
Given that, how would you connect it to a 5V Uno?
BMP280 Digital Pressure Sensor
Given that, how would you connect it to a 5V Uno?
I've updated the circuit in reply#7 to show voltage levels. MOSI, SCK and CS will each have 9mA load for the voltage divider.
Thank you.
I'm not just looking for a recipe but hoping to understand the tradeoffs. The circuit I posted is actually used on a shield that I have. So I wonder what the designers were thinking when they chose that particular approach. Your circuit would have a faster response time but much higher current draw, even if the device were put to sleep or powered down -- is that correct? Would the voltage dividers have any effect on the maximum clock rate for other devices sharing the SPI bus?
Would the voltage dividers have any effect on the maximum clock rate for other devices sharing the SPI bus?
Yes.
In effect it magnifies stray capacitance and slows down edges.
So I wonder what the designers were thinking when they chose that particular approach.
Going for cheap and cheerful with the minimum they could get away with, or else they are not very good designers. Just because something is produced commercially doesn't mean it is a good design or good practice.
I guess it would depend on device's characteristics, the application, cost, power considerations, speed, interface cable length or even trace length on the PCB, loading (number of devices on the bus), etc.
The voltage divider circuit would be too power hungry for battery/portable applications. It shouldn't effect the maximum clock rate for other devices as the load is resistive (I've used lower resistance values to gain speed at the expense of extra power draw). The series resistance part of the divider would have the benefit of reducing "ringing" or signal reflection on the lines at higher speeds. Intel Galileo uses 27Ω series resistance on its SPI lines, the Atmel SAM3X has built on-die series resistors of 36Ω for all of its I/O.
The best solution would be an appropriate buffer/level shifter IC if bus loading, power and speed are prime design criteria, but it would add to the cost.
I've been happily using these...
Under Technical Details are links to whitesheets that explain how it works.
The caveat is you will very likely have to buy a breakout board or learn to solder tiny parts.
Edit: I misunderstood the goal. No soldering or breakout boards necessary.