I saw that the SPI communication has shift registers in it. Where a single clock edge is enough to shift a bit from the lines to the registers. As shown:
Considering mode zero. It states that Shift transmits data on the leading clock edge, and latch on the trailing edge. What do they mean by shift and latch? On a single edge, both can happen like sifting from the MOSI to slave and MISO to master. All this occurs in sing edge. Then what do they mean by this???
SPI is a transport protocol, so i think that "shifting the bit" means merely a transfer the bit from master to slave or wise versa.
Sorry, i am not sure that understand your question.
"Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize". These are from the datasheet
The connecting wire between SPI-Master and SPI-Slave has transmission delay which must be taken into account by both Master and Slave for the successful sampling of the arrived signal.
The RISING Edge of the SCK signal pushes out data from Master to Slave and from Slave to Master. It is the FALLING Edge of SCK signal that latches (stores) the data bit going from Master to Slave over the MOSI line and the data bit coming from Slave to Master over the MISO line. This is to account for the transmission delay of the connecting cable.
Yes!
If you are using 1 MHz SCK, then the FALLING Edge of the clock would appear at 0.5 us later. If there would be no line inductance-capacitance, then the signal would transmit instantly at the speed of light.
Sir this is fine but in order to shift a bit out,it will always take a bit in at the same time. Now suppose MOSI and MISO lines have 1,1 on them and I give a clock rising edge. Then MISO lines value 1 will be put in the shift register,a bit value from same register will move to MOSI line. The previous MOSI line value 1 will shift to the slave shift register,and final bit of slave back to MISO line. All this occurs in one rising clock edge. No opposite edge is used. Kindly correct me if I am wrong.
Even then there has to be some data on the MOSI and MISO either 0 or 1. The lines cant be idle. If I consider them zeros and on the positive clock the values go out, then won't they create a bus contention case where the previous zero wasn't taken in by the next register and the new value came on the line.
Bus contention is a situation where more than one device wish to assert data on the same communication line. In SPI Port, the communication network is a circulating type; there is no question of bus contention.
Look at Fig-1 of post #7, the SCK signal is connected with the CLK-pin of both the shift registers (the SPDR Registers) of Master and Slave. So, the data must be circulating unless the MOSI/MISO line is broken.
yes, they must be circulating and should circulate at the same time, not that I send half values out with the previous values still waiting to go in with the negative edge. I am just taking it intuitively.
If you are owning two Arduino UNOs, then perform an experiment to exchange int type (2-byte) data between SPI-Master and SPI-Slave in order to understand the functioning of the SPDR (shift) Registers.
