So if my understanding is correct these ICs are used when multiple devices are sharing the same data bus. so for example if i had 5 devices that needed to use my I2C i could use some these ICs and wire all them up and allow one at a time to use the bus, but cant this all be done through proper coding with out the need of an external component?
however the latch's memory feature seems a bit more handy , in that when you return to it , it retains the values received while it was ...dormant.. i guess. but how much can it store and for how long, is it voltaile? i guess this is specific to the component used.
and there are transceivers , these allow for bidirectional transmission , but then again i keep thinking this is all possible through code...right? i just do not see their purpose ,
i mean if you have 5 sensors all sharing one data bus, you obviously can only read from one at a time, so you just control which one is on at a certain to then turn it off and then turn on the next one....
please enlighten me with some real world applications where they are absolutely needed and cannot be worked around
if i had 5 devices that needed to use my I2C i could use some these ICs and wire all them up and allow one at a time to use the bus,
No that wouldn't work because the I2C data line is bi-directional and these latches are not.
but how much can it store and for how long,
1 Bit for as long as power is applied
is it voltaile?
Yes
but then again i keep thinking this is all possible through code...right?
No, no amount of code can reduce signal line impedance.
i mean if you have 5 sensors all sharing one data bus, you obviously can only read from one at a time, so you just control which one is on at a certain to then turn it off and then turn on the next one
No because when a sensor has no power it's output looks like a diode thus shorting out the sensor that is turned on.
with some real world applications where they are absolutely needed and cannot be worked around
Memory and I/O using several chips on a bus system.
The classic use for an octal bus transceiver was back in the days when microprocessors came in 40pin DIP packages. The 74LS245 et al would interface between a RAM module and the data bus, between an IO device and the data bus, basically everything on the data bus except the processor (which had its own bus driver built in).
The system had to be designed to ensure that no more than one bus transceiver was driving the bus at once and all the others were tri-stated. Typically each bus client only accessed the bus when the address bits matched its address (certainly for RAM, sometimes for IO (memory-mapped IO)) Looking at schematics for early 6502, 6800, Z80 computer designs will show bus transceivers and latches everywhere...
Some devices used a latched bus receiver to hold on to the value after the microprocessor performed a write cycle.
The kind of busses commonly used for sensor arrays tend to use open-drain drivers and pull-up resistors, so there is no danger of burning out a driver if two devices write the bus simultaneously (in fact the OneWire bus relies on this wired-AND effect). OneWire and two wire busses are like this.