1. Referring to Fig-1, at Vcc = 5V, the VIL = 1.5 V which means that a healthy input device must assert <=1.5V so that the MCU will recognize it as LOW whenever its turn comes to execute the code: int y = digitalRead(DPin).
2. Suppose that the MCU is not yet ready to execute digitalRead() operation and
the VIL = 1.4 V has caused the Schmit Trigger (Fig-2) to record LOW at its output at time t1.
3. Given that Vhys = 0.25 V (Fig-1). Does it mean that the VIL level could slowly be increasing to 1.65 V (1.4 + .25) by environmental noise, but the Schmit Trigger will still be recording LOW at its output? The MCU will read LOW when it performs int y = digitalRead() operation at time t2.
4. At the absence of the Schmit Trigger, what would be the value of y in Step-3? My answer is: inderterministic.
5. What could be the maximum value of Vhys -- the hysteresis width? My answer is: VIH - VIL = 3.5 - 1.5 = 2 V.
6. VIH is threshold of the second switching point to detect HIGH logic.
Comments, corrections, and suggestions are welcome from the veteran members of this forum.
In the example shown it is to isolate the input pin from the logic when the part is put to sleep. Here is a general explanation:
ICs Use Transmission Gates to solve key problems in both digital and analog designs:
Bidirectional switching: Current can flow in either direction, unlike standard logic gates.
Examples:
Analog multiplexers
Bus switches
Sample-and-hold circuits
RAM cell wordline access
Near-zero distortion (analog)
They are used in:
Audio switching ICs
ADC sample switches
Switched-capacitor filters
Because on-resistance is low and linear.
Pass full logic levels (digital)
A single NMOS would not pass a full '1' reliably.
A single PMOS would not pass a full '0'.
But both together → almost no level loss.
Where you can find Transmission Gates:
Common examples inside ICs:
74HC4066 / CD4066 → analog switches built from transmission gates
Multiplexers / Demultiplexers
Flip-flops (D latch inside uses TGs)
Clock gating circuits
CMOS bus switches
On-chip analog routing
Nearly every CMOS chip uses TGs somewhere inside.
Electrical Characteristics
Key parameters of a transmission gate include:
R_on (on-resistance): typically 30–200 Ω this being process dependent
C_off (off-capacitance): a few pF
Charge injection (analog distortion)
Low leakage when OFF
Maximum speed limited by gate capacitances
This is a few of the many. Personally I do not know of any processors that do not use them in one form or other.
Thank you for asking me the question and the subsequent answer you have provided.
I know that the sleep instruction cuts power and clock (depending on the sleep mode) from the digital IO module. Now, I know that it also opens the transmission gate to isolate the Schmit Trigger from the input line/device to reduce power consumption.
@JohnLincoln
I did not make any negative comment on your referred post; rather, I just asked a simple question on your experimental values for VIL, VIH, VOL, VOH.
In this thread, you see my ignorance on the topic I have initiated. I am using my liberty to associate the forum members to convert my ignorances into knowledge for onward delivery yo my students.
Let's consider a slowly rising voltage applied to a pin.
The point where the digital output of the Schmitt trigger actually goes from '0' to '1' is determined by the circuit connected to this pin, in this device, at this temperature, at this supply voltage, all of which are variable.
The number VIHmin given in the datasheet is the voltage above which the manufacturer guarantees will be seen as '1'.
Something similar for the lower threshold.
The manufacturer has wanted to give some noise margins to their MCU device. Accordingly, they have incorporated, with the input pin, a Schmitt Trigger with hysteresis indicating that it has two distinct switching points.
The following diagram (Fig-1) taken from net explicity explains the role of Schmitt Trigger to extract correct digital signal from a otherwise noisy signal.
In Fig-1, the Schmitt Trigger records HIGH when input signal >= VUT (=VIH, upper threshold voltage). At some points, we observe that input signal has gone down below VUT (but > VLT), but the Schimitt Trigger is still maintaining its previous HIGH state by virtue of its memory created by feeding positive feedback in an inverting amplifier (Fig-2).
If the transition of the Schmitt trigger is very close to the edge of the clock, the state of the dataline is poorly defined.
Imagine the transition occurring while the gate to the databus is open.
It also allows generation of interrupts.
Please paraphrase the above so that I (non-native English speaker) clearly understand the intended meaning. To me, the input signal to a Schmitt Trigger is a bit fuzzy rather than a pure clock.
