I would like to share the driver-display connections so that you can correct my "init" commands (attached as well) if you find something wrong.
static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_ADR(0), /* instruction mode */
0x0ae, /* display off, sleep mode */
U8G_ESC_ADR(0), /* instruction mode */
0x0b3,
U8G_ESC_ADR(1), /* data mode */
0x091, /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
U8G_ESC_ADR(0), /* instruction mode */
0x0ab,
U8G_ESC_ADR(1), /* data mode */
0x001, /* Enable Internal VDD Regulator */
U8G_ESC_ADR(0), /* instruction mode */
0x0a2,
U8G_ESC_ADR(1), /* data mode */
0x000, /* display offset, shift mapping ram counter */
U8G_ESC_ADR(0), /* instruction mode */
0x0a1,
U8G_ESC_ADR(1), /* data mode */
0x000, /* display start line */
U8G_ESC_ADR(0), /* instruction mode */
0x0fd, /* lock command */
U8G_ESC_ADR(1), /* data mode */
0x012, /* unlock */
U8G_ESC_ADR(0), /* instruction mode */
0x015, /* setting column address */
U8G_ESC_ADR(1), /* data mode */
0x01c, /* start at column 0 */
0x05b, /* end column */
U8G_ESC_ADR(0), /* instruction mode */
0x0a0, /* Set Re-Map / Dual COM Line Mode */
U8G_ESC_ADR(1), /* data mode */
0x016, /* was 0x014 0x16=0b 0001 0110*/
0x011, /* was 0x011 0x11=0b 0001 0001*/
U8G_ESC_ADR(0), /* instruction mode */
0x0c1, /* contrast */
U8G_ESC_ADR(1), /* data mode */
0x09f,
U8G_ESC_ADR(0), /* instruction mode */
0x0c7, /* Set Scale Factor of Segment Output Current Control */
U8G_ESC_ADR(1), /* data mode */
0x00f,
U8G_ESC_ADR(0), /* instruction mode */
0x0ca, /* multiplex ratio */
U8G_ESC_ADR(1), /* data mode */
0x03f, /* 1/64 Duty (0x0F~0x3F) */
//grayscale qui-------------------------------------------------------------
U8G_ESC_ADR(0), // instruction mode
0x0b8,
U8G_ESC_ADR(1),
0x001,
0x00d,
0x019,
0x025,
0x031,
0x03d,
0x049,
0x055,
0x061,
0x06d,
0x079,
0x085,
0x091,
0x09d,
0x0a9,
0x0b4,
U8G_ESC_ADR(0), /* instruction mode */
0x000, /* turn on gray-scale */
//fine grayscale-----------------------------------------------------------
U8G_ESC_ADR(0), /* instruction mode */
0x075, /* row address setting */
U8G_ESC_ADR(1), /* data mode */
0x000, /* start address */
0x03f, /* end address */
U8G_ESC_ADR(0), /* instruction mode */
0x0b1, /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
U8G_ESC_ADR(1), /* data mode */
0x0e2,
U8G_ESC_ADR(0), /* instruction mode */
0x0b4, /* Display Enhancement A */
U8G_ESC_ADR(1), /* data mode */
0x0a0,
0x0fd,
U8G_ESC_ADR(0), /* instruction mode */
0x0b5,
U8G_ESC_ADR(1), /* data mode */
0x000, /* imposto GPIO era 0x011, datasheet schermo 0x000 */
U8G_ESC_ADR(0), /* instruction mode */
0x0b6, /* precharge period */
U8G_ESC_ADR(1), /* data mode */
0x008,
U8G_ESC_ADR(0), /* instruction mode */
0x0bb, /* precharge voltage */
U8G_ESC_ADR(1), /* data mode */
0x01f,
U8G_ESC_ADR(0), /* instruction mode */
0x0be, /* vcomh */
U8G_ESC_ADR(1), /* data mode */
0x007,
U8G_ESC_ADR(0), /* instruction mode */
0x0d1, /* Display Enhancement B */
U8G_ESC_ADR(1), /* data mode */
0x082, /* era 0x082|0x020*/
0x020,
U8G_ESC_ADR(0), /* instruction mode */
0x0a6, /* normal display */
U8G_ESC_ADR(0), /* instruction mode */
0x0a9, /* exit partial display */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_ADR(0), /* instruction mode */
0x0af, /* display on */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
