Vidor 4000 - FPGA programming/interaction

Dear Forum,
I'm new to Arduino MKR Vidor 4000, I've already successfully uploaded an VHDL program from a tutorial into the FPGA, using Quartus software. My intention now is to create my own VHDL code and from SAMD21 send data to the FPGA to be processed. Is that possible and is there any tutorial or guide to me to follow?

Thanks all

(sorry if my idea is confuse)

Arduino does provide a tutorial, though it's for Verilog instead of VHDL:

If you need also ByteBlaster "clone" library in same scetch then I recommend to use serial for commonication. When using blaster then you have to keep loop short. Too long time taking loop will cause BSOD.

I was planning to do example but I don't currently have time. Haven't touched my own vidor board in 4-5 weeks.

The VHDL tutorial only demonstrates how to program in Verilog/VHDL not how to integrate it with the MKR vidor 4000.

What i pretend to study is, implement my own VHDL code and send it to the FPGA, it should execute image processing. To do so, i need to send the image itself to the FPGA. I've followed a guide (which I link in the end) that uses the Quartus software, creates a .h (bitstream file and inverts it) and integrates it in the arduino using:

attribute ((used, section(".fpga_bitstream")))
const unsigned char bitstream = {
#include "app.h"

Unfortunately I've no idea how this works. My main doubts are, with this it is possible to load my VHDL code to the FPGA and it is also possible to load different VHDL codes during the elapse of the arduino program. And can i load an image to the FPGA through the arduino, if not through the arduino, from a specific folder.

Thanks all.

Hello CarlosGarcia96,

unfortunatly (and I don't know why) my blog is offline for the moment.

In the first article of my blog (you can find an update version here : Arduino MKR Vidor 4000 et FPGA
I explained how the FPGA bitstream is uploaded in the FPGA.

For VHDL programmation, you should just rewrite the top level verilog file in VHDL, and add your own code


There are Vidor template projects in github. These have FPGA device select and pin mapping is done.

This does have verilog topmodule so you can use this as wrapper or create new top module. I recommend to use it as wrapper.

This github also contains scripts to create that library for arduino (includes app.h file). You create library from your FPGA design and import it to arduino IDE. For this you need go compiler from google (need to compile byteswap command)

After running command "" in NIOS II command shell in project folder (cygwin linux installed with quartus)
Last phase of this script calls and this will create library to use with Arduino IDE.

When you upload arduino scketch that contains app.h then programmer part of arduino will detect this and give it to address that's outside of SAMD21 FLASH area and Vidor bootloader will detect it and write it to FPFA configuration memory after golden image.

There are few project templates.

  • Full "empty" only with device type, pin outs and port mapped top module.
  • Project with basic peripherals. This project have qsys file that contains peripheral modules and nios ii with mailbox for commonication to FPGA. This use JTAG for data communication so you can't use signaltap.

Then there are example project from current Vidor library deliveries if you want to study.

I'm planning to create project where we are using USB blaster clone sketch for signal tap and uart for data link to FPGA. In this project there are separated. Current status is that I don't have enough time for creating this. Maybe in few months I try to do this and I have to do some specificatoions first for that datalink.

Would freq counter to be good example? Maybe up to 100 MHz

Hi CarlosGarcia96,

I am trying to develop my verilog modules as Qsys components.
On the way to develop the modules, I wrote an Arduino class and its example sketch to use the "SPI Slave to Avalon Master Bridge" IP core.

By using this class with the "SPI Slave to Avalon Master Bridge" IP core in your Qsys design, you can access (read/write) to any Qsys components mapped on Avalon bus via SPI from SAMD (or an external SPI master).
It does not use a MailBox core and also not need a NIOS II softcore because any memories (SDRAM, QSPI flash) and memory mapped IOs can be accessed from SAMD via the bridge.

Instead of SPI, JTAG can be used, but I am not familiar to JTAG, so I chose SPI.
A disadvantage of using SPI is that 4 pins (MOSI, MISO, CLK and Slave Select (SS)) on a Vidor 4000 board are occupied.

The class (AvalonMM) and sketch are here:

Entire project is here:

My project is just WIP, so please note that:

  • All codes are in "develop" branch, not in "master" branch yet, and
  • I tested using a USBBlaster and my USBBlaster_AvalonMM sketches only, i.e. I have not tested through an "app.ttf".

Brief instructions are as follows:
(If you have already prepared compilation environment, start from the step 8.)

  1. Install the Go language.
  2. Clone the "develop" branch of my project.
  3. Run the "NIOS II Command Shell".
  4. Move to the cloned directory, and run "chmod -R a+rw *".
  5. Move to "TOOLS/scripts", and run "./".
  6. Move to "TOOLS/makeCompositeBinary", and execute the command "go build -o makeCompositeBinary make_composite_binary.go".
  7. Add "TOOLS/scripts" to your PATH. (You don't have to add "TOOLS/makeCompositeBinary" to the PATH.)
  8. Move to "projects/MKRVIDOR4000_gdev", and build the project by "".
  9. Detach anything from D7, D8, D9 and D10 pins which are used between SAMD and FPGA for SPI.
  10. Open "projects/MKRVIDOR4000_gdev/software/examples/USBBlaster_AvalonMM/USBBlaster_AvalonMM.ino" from ArduinoIDE, and program it to your Vidor 4000.
  11. Open the serial console on ArduinoIDE.
  12. Open "projects/MKRVIDOR4000_gdev/build/MKRVIDOR4000_gdev_lite.qpf" from Quartus Prime 18.1 Lite.
  13. Download the bitstream (MKRVIDOR4000_gdev_lite.sof) to the Vidor 4000.

When the download is finished, the sketch on SAMD automatically detects the "SPI Slave to Avalon Master Bridge" is responded, then

  • Writes 0x00 to address 0x0000_0000 which is the first byte of the SDRAM on the Avalon bus in Qsys,
  • Dumps the first 256 bytes of the SDRAM,
  • Writes 0x12 to 0x0000_0000,
  • Dumps again (you can see the first byte is changed to 0x12), and
  • Blinks the D0 pin on the Vidor 4000 by writing 1 and 0 alternately to the PIO register (0x0080_0000) in Qsys.

Hi tksm372,

Before all, thanks for your help. I just encountered one problem (or maybe I'm just doing it wrong). When you mean download the bitstream .sof, it's to open the project in Quartus and run "compile design"?
If so, it says the stp2.stp file in output files is missing and I see no update in the previous MKRVIDOR4000_gdev_lite.sof that was already in the folder.

Also, and correct me if I'm wrong, the goal is to generate a .ttf file and attach it to the project.

Again, thanks for your support.

Hi CarlosGarcia96,

When you mean download the bitstream .sof, it's to open the project in Quartus and run "compile design"?

Yes, that's right.

If so, it says the stp2.stp file in output files is missing and I see no update in the previous MKRVIDOR4000_gdev_lite.sof that was already in the folder.

Thank you for your report, it is my mistake.

The stp2.stp file is a config file for the "Signal Tap Logic Analyzer". I debugged my design using it, and I forgot to disable it in the project setting before push my project to GitHub.

I updated the repository, so please pull the update.

You can manually disable the "Signal Tap Logic Analyzer" by the following steps:

  • Open MKRVIDOR4000_gdev_lite.qpf in the build directory by the Quartus.
  • Right-click the "MKRVIDOR4000_top" in the Project Navigator pane, and choose the "Settings..."
  • Select the "Signal Tap Logic Analyzer" from the "Category" list, and uncheck the "Enable Signal Tap Logic Analyzer".