Is the OLED configured for SPI? BS0, BS1 and BS2 all connected to GND?
Writing the software driver: You could use the ssd1327 constructor as a starting point.
Locate file u8g_dev_ssd1327_96x96_gr.c and have a look at the init sequence:
static const uint8_t u8g_dev_ssd1327_2bit_96x96_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x0fd, 0x012, /* unlock display, usually not required because the display is unlocked after reset */
0x0ae, /* display off, sleep mode */
0x0a8, 0x05f, /* multiplex ratio: 0x05f * 1/64 duty */
0x0a1, 0x000, /* display start line */
0x0a2, 0x060, /* display offset, shift mapping ram counter */
//0x0a2, 0x04c, /* NHD: display offset, shift mapping ram counter */
0x0a0, 0x046, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
//0x0a0, 0x056, /* NHD: remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
0x0ab, 0x001, /* Enable internal VDD regulator (RESET) */
0x081, 0x053, /* contrast, brightness, 0..128, Newhaven: 0x040, LY120 0x053, 0x070 seems also ok */
0x0b1, 0x051, /* phase length */
0x0b3, 0x001, /* set display clock divide ratio/oscillator frequency */
0x0b9, /* use linear lookup table */
#if 0
0x0b8, /* set gray scale table */
//0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
#endif
0x0bc, 0x008, /* pre-charge voltage level */
0x0be, 0x007, /* VCOMH voltage */
0x0b6, 0x001, /* second precharge */
0x0d5, 0x062, /* enable second precharge, internal vsl (bit0 = 0) */
#if 0
// the following commands are not used by the SeeedGrayOLED sequence */
0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
0x086, /* full current range (0x084, 0x085, 0x086) */
0x0b2, 0x051, /* frame frequency (row period) */
0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
#endif
0x0a5, /* all pixel on */
//0x02e, /* no scroll (according to SeeedGrayOLED sequence) */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display mode */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* all pixel on */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display mode */
0x015, /* column address... */
0x008, /* start at column 8, special for the LY120 ??? */
0x037, /* end at column 55, note: there are two pixel in one column */
0x075, /* row address... */
0x008,
0x05f,
This sequence has to be modified for your display. Best would be to take over commands from your sample code.
For example change
0x0a8, 0x05f, /* multiplex ratio: 0x05f * 1/64 duty /
to
0x0a8, 0x01f, / multiplex ratio: 0x01f * 1/64 duty */
because this is what is used in the sample code.
All in all, you have to take over the init code from the example to the u8glib driver.
Assuming the hardware is correct (which i can not check), then you may see some activity.
It is also a good idea to use the all pixel on and off commands to check proper functionality.
Oliver
Oliver