It is a simulation of SPICE.
Even if the gate and source are directly connected, still current flowed while charging the output capacitance shown in the figure above.
This phenomenon is caused by parasitic capacitance, so the big MOSFET is used, the more noticeable it becomes.
How do we allow it to happen without passing power? A device before and / or after?
What does the simulation do if the gate is grounded (P-MOS always on) instead of connected to the Arduino digital pin?
Since charging of this capacitor starts when the circuit is completed, even if a simply switch is installed in the subsequent stage, and after the gate voltage is raised sufficiently current will flow the moment the switch is connected.
P-MOS pass through the current.
What if that switch had a normally closed position to ground?
There is a possibility that the charge current of the P-MOS parasitic capacitances can be bypassed, but since the switch control transistor even have the same phenomenon, it is necessary to be careful when selecting the component.
In addition, that switch creates a short-circuit if it malfunctions when P-MOS is ON, that has the potential to cause a major accident.
Yeah, I was reading about that. The issue with bypassing it is that when you need it you've bypassed it.
No, I think this is like lightening, we have to let a blip of power from the source to the drain of Q2 and then to have that blip diverted to ground. Once the blip has passed the proper circuit should be closed. Something like a relay connected as a router (backwards), but that remains closed to the proper circuit unless the battery is disconnected.
What about a tiny ultra low current battery on the board? Like an RTC battery.
It's only responsibility would be to hold the gate high with a tiny bit of current.
Bonus point if was able to be charged by the primary current.
As shown in #240 and #242, even if the gate is always HIGH, (small) current flows to charge the MOSFET's Cds.
EDIT:
However, Cds is much smaller than Ciss, so it may be negligible compared to the gate rise delay.
Oh, I might have misunderstood where to install the capacitors.
When installed between the source and the gate, it provides a momentary gate charging current that bypasses the pull-up resistor, which has the effect of accelerating gate ramp-up.
What happens if I install a 1u ceramic capacitor with a low ESR?
The charging current of the Cds remains as before, but it should help to make the gate HIGH faster than the pull-up resistor.
Can you show me, please? Just the minimum.
I've gone through so many configurations that I've confused myself.
Watch it be the thing I suggested at first but neglected to draw.
Just add it in parallel to R2 as he says.
And the lesson I learned again was to draw the picture when I ask the question. I would have used a polarized cap but I poorly stated it at some point.
Ah well, at least the issue is solved.
Thank you so much.
Hope you're having an awesome day 
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So, much better, but still a very narrow spike?
With the cap, Vmax is still equal to Vbatt?
Is this good enough or is there more work to do?
This shows the current when charging the parasitic capacitance between the drain and the source, so it cannot be eliminated.
No spikes are generated that exceed the battery voltage.
This graph refers to the current scale on the right side except for the blue voltage line.
I think this is well enough.
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Learning the usage of SPICE simulator is useful for circuit analysis. 
I've learned a lot in the past 2 months. I'm going to focus on KiCAD for a while until I'm good, making projects along the way. Then I'll get to SPICE.
It will be a better way to test my relay computer concepts. Certainly cheaper than buying and running ten thousand relays, but I will miss hearing the clicks.
In the past, I have been asked to do a project to play relay sounds on the turn signals of a car that has been replaced by LED lights and SSRs and has no "click" sound. 