The moment the PMOS switch is turned on, the inrush current is too large and the PMOS burns out

When it comes to MOS tube burnout, it is usually because it is not working in the SOA workspace, and there is also a case where the MOS tube is overcurrent.

For example, the maximum allowable current of the PMOS transistor in this circuit is 50A, and the maximum current reaches 80+ at the moment when the MOS transistor is turned on, then the current is very large.
At this time, the PMOS is over-specified, and we can see on the SOA curve that it is not working in the SOA range, which will cause the PMOS to be damaged.
So what if you choose a higher current PMOS? Of course you can, but the cost will be higher.
We can choose to adjust the peripheral resistance or capacitor to make the PMOS turn on more slowly, so that the current can be lowered.
For example, when adjusting R1, R2, and the jumper capacitance between gs, when Cgs is adjusted to 1uF, The Ids are only 40A max, which is fine in terms of current, and meets the 80% derating.
(50 A * 0.8 = 40 A).
图片2
Next, let's look at the power, from the SOA curve, the opening time of the MOS tube is about 1ms, and the maximum power at this time is 280W.
图片3
The normal thermal resistance of the chip is 50°C/W, and the maximum junction temperature can be 302°F.
Assuming the ambient temperature is 77°F, then the instantaneous power that 1ms can withstand is about 357W.
The actual power of PMOS here is 280W, which does not exceed the limit, which means that it works normally in the SOA area.
Therefore, when the current impact of the MOS transistor is large at the moment of turning, the Cgs capacitance can be adjusted appropriately to make the PMOS Working in the SOA area, you can avoid the problem of MOS corruption.

The typical burnout mode for a MOSFET is it overheats some cells and fry's. What you need is to drive it properly and keep it out of the linear (ohmic) portion of the Vgs curve. The MOSFET is composed of lots of individual parallel cells and they are not all the same, so some will get hot quicker then other causing a hot spot prone to fail.

The gate is capacitive and a resistor keeps it in the ohmic area longer because of the RC time constant. I like to keep my gate resistors below 10 Ohms when driving heavy loads and get them into complete saturation as fast as possible. When in doubt increase the gate drive voltage. There are not many MOSFETs that are fully enhanced with a 5V gate drive.

Another trick is paralleling them, be sure they share the same heat sink and are reasonably the same temperature. The warmer they get the higher there RDSon. This will thermally help them share the load.

What is causing the inrush current?

+1
Keep it out of the ohmic region.
Slow switching is NOT the answer, which makes the whole design wrong.
Can't you use an N-channel fet in the ground line, with a proper gate driver.
PWM ramping could be the answer to that inrush current, but you didn't tell us what kind of load you're switching.
Leo..

Remove C1 and R2 for faster switching.

Hi, @vbsemi
Welcome to the forum.

Do you actually have this happening in real life?
If so, what is the load that you are supplying current too?

Some bigger images would be good too.


What is the part number of the PMOS?
Please post a link to data/specs.
image

Thanks.. Tom.. :smiley: :+1: :coffee: :australia:

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  • Don't much like C1 and the value of R2 is quite large.
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Why should an overcurrent surge happen at switch on? That depends on the load, which you havent shown. You also havent shown the voltages on the schematic.

Also thermal resistance and power calculations are appropriate for events of a long duration, I'm not sure they are appropriate for such short term events.

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Is that control signal intended for the occasional switching of a high current load or is it high frequency PWM or what ? The circuit design seems more suitable for the occasional switching use case.

The part numbers on the schematic are unreadable.

Now that vbsemi has filled out his profile and gained his autobiographer badge, we can see that he is in fact a MOSFET manufacturer.

Just saying.

So this is SPAM..

Tom.. :smiley: :+1: :coffee: :australia:

Well, the Mosfet in the schematic is this: https://www.mouser.com/datasheet/2/427/SI4425DY-254872.pdf from Vishay not vbsemi so I'd not say it is blatant advertising.
If he can justify his circuit and analysis then I'd say that is OK.

Thank you for your reply. Yes, we mainly output circuit design and applications of MOSFETs and other devices. If you need test samples, please send us a private message!:smiley:

What is your equivalent (or better because these are getting old) of the AO3400 and AO3401 mosfets which are often used in hobby designs? That is: Medium power. Low RDS(on) quoted at a low voltage.

Suitable for load switching

This is a hypothetical situation where a surge occurs. :smiley:

Yes. that is what I meant.

It could be a relay, a boost converter, a small motor, an H-bridge etc.

For medium power applications with low RDS(on) at low voltages, consider MOSFETs like the VB1330 and VB2355.

Advertising...

Tom.. :smiley: :+1: :coffee: :australia:

You can see that I asked him for a specific example out of that product range. It is not surprising that the manufacturer's name appears on any search for documentation.

I have seen advice that in such a case each MOSFET should have its own gate resistor.

I have seen criticism of the design of off-the-shelf paralleled MOSFET driver modules that do not.

What I was able to understand of the matter whilst googling, it just makes sense to have a gate resistor for each.

So I ask opinions here.

TIA

a7