I hope to use the UNO R4 SPI to read an external ADC, and I would like to be able to clock the reads as fast as the part can possibly do it.
For completeness, I'll mention that the ADC is an MCP33131D. It requires a 700nsec sampling time and the transfer time for 16 bits at 12MHZ should be 1.3 usec. So altogether that is 2usec. We might expect to clock the ADC at something close to 500 KSPS.
Okay, here is the code for a (perhaps idealized) single 16 bit read, followed by an oscilloscope trace for the CNVST pin (lower trace) and the SPI clock (upper).
Notice that from the trailing edge of the CNVST there is 2.5 usecs before the transfer starts, and then the transfer occurs not as a single 16 bit transfer but rather as two 8 bit transfers separated by yet another 1.2usecs. That is a huge problem.
digitalWrite(CNVSTPIN,HIGH;
DELAYNANOSECONDS(700)
digitalWrite(CNVSTPIN,LOW);
dataword = SPI.transfer16(0xFFFF);
Now for comparison, here is what that same operation looks like in the Teensy 4.0. The second image is with scope set to a faster time scale to show you that it is really a single 16 bit transfer and the setup time is actually just a little under 180 nsecs.
As it turns out, the NXP part has a setting to control the number of bits per transfer. Do we have that in the RA4M1?
The setup time might be consistent with the processor clock speeds (600MHZ/48MHZ = 12.5, and 2.5usec/180nsec = 13).
But then with the slower clock, that means that for loops, we might want to factor out some of the SPI setup and just do whatever is the minimum to trigger each transfer.
Recall (at the top), we need to toggle a line between transfers, so we cannot just do this as a long contiguous block transfer.
Any help?