I was making tests on my Portenta ADC readings and noticed a huge voltage drop on my input pin when I Enable the ADC ( the signal is litteraly divided by two). I have been searching for a reason for a few days already and I came accross a few answers from people encountering these kind of issues (not always on the same board as me) :
-Use capacitors, I tried every possible position adviced on forums, like between the Vref and the Gnd, between the Analog input pin and the Vref, and on the input pin to counter the internal capacitor effects. None of these options worked for me.
-Some say it is because your input pin is not defined as analog and the pull up and pull down are not disabled but analog mode is the default setup of the register and acciording to the following schematics in Analog mode there is no pull down or pull up :

(It says to be High Impedance does it mean the capacitors I used to reduce the said impedance were not up to par?)
Also since I am using an additional function of the GPIO pin (see table below) which is ADC2_IN0 I should not have to set up anything for the GPIO and only go through the peripheral register to configure the Input.
-Last solution I found online use an OPAMP in follower mode, I have not tried this one yet and I am on it. Since I don't have an OPAMP with me I ll try using the one from the board.
Here is the code I use to setup the ADC if someone sees something likely to cause me trouble?(some of my trial and errors are commented in it)
void ADC_Init(void) {
/*******************Clocks**************************/
SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN_Msk); //GPIOA clock
delay(1000);
SET_BIT(GPIOA->MODER, GPIO_MODER_MODE0_0 | GPIO_MODER_MODE0_1);
//GPIOA->MODER=0xFFFFFFFF;
//CLEAR_BIT(GPIOA->PUPDR, GPIO_PUPDR_PUPD0_0);
//CLEAR_BIT(GPIOA->PUPDR, GPIO_PUPDR_PUPD0_1);
//pinMode(A0, INPUT);
SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN_Msk); //SYSCFG clock
delay(1000);
//CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_PA0SO_Msk | SYSCFG_PMCR_PA1SO_Msk | SYSCFG_PMCR_PC2SO_Msk | SYSCFG_PMCR_PC3SO_Msk);
SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN_Msk);//SYSCFG_PMCR_BOOSTVDDSEL |
delay(1000);
// SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN_Msk); //RTCAPB clock
// delay(1000);
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN_Msk); //ADC12 clocks
delay(1000);
// SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN_Msk); //GPIOA clock
// delay(1000);
/********************Port config************************/
// __HAL_RCC_ADC12_FORCE_RESET();
// HAL_Delay(1);
// __HAL_RCC_ADC12_RELEASE_RESET();
// SET_BIT(GPIOC->MODER, GPIO_MODER_MODE4_0);
// SET_BIT(GPIOC->MODER, GPIO_MODER_MODE4_1);
// CLEAR_BIT(GPIOC->PUPDR, GPIO_PUPDR_PUPD4_0);
// CLEAR_BIT(GPIOC->PUPDR, GPIO_PUPDR_PUPD4_1);
delay(1000);//PA0_C in analog mode
// pinMode(A1, OUTPUT);
// pinMode(A2, OUTPUT);
// pinMode(A3, OUTPUT);
// pinMode(A4, OUTPUT);
// pinMode(A5, OUTPUT);
// pinMode(A6, OUTPUT);
delay(1000);//PA0_C in analog mode
/********************ADC voltage regulator***************/
CLEAR_BIT(ADC2->CR, ADC_CR_DEEPPWD_Msk); //END DEEPPWD
SET_BIT(ADC2->CR, ADC_CR_ADVREGEN_Msk); //ENABLE ADC VOLTAGE REG
//while((ADC2->ISR & 12)!=1){}
delay(1000);//WAIT VOLTAGE REG
/******************ADC clock*****************************/
SET_BIT(ADC12_COMMON->CCR, ADC_CCR_CKMODE_0 | ADC_CCR_CKMODE_1 );//
/*******************ADC Prescaler************************/
//SET_BIT(ADC12_COMMON->CCR, ADC_CCR_PRESC_0 );//| ADC_CCR_PRESC_1
// while ((ADC2->CR & ADC_CR_ADDIS)) {
// digitalWrite(LEDR, LOW);
// }
// digitalWrite(LEDR, HIGH);
/*******************Input Mode***************************/
CLEAR_BIT(ADC2->DIFSEL, ADC_DIFSEL_DIFSEL_0); //Single Ended
/********************ADC calibration*********************/
CLEAR_BIT(ADC2->CR, ADC_CR_ADCALDIF_Msk);
SET_BIT(ADC2->CR, ADC_CR_ADCALLIN_Msk);
SET_BIT(ADC2->CR, ADC_CR_ADCAL_Msk);
while (ADC_CR_ADCAL & ADC_CR_ADCAL_Msk != 0) {}
//while((ADC2->CR & 31) ==1){}
/**********************ADC BOOST*************************/
SET_BIT(ADC2->CR, ADC_CR_BOOST_0 | ADC_CR_BOOST_1);
/*******************ADC Enable***************************/
SET_BIT(ADC2->ISR, ADC_ISR_ADRDY_Msk);
SET_BIT(ADC2->CR, ADC_CR_ADEN_Msk);
while (ADC_ISR_ADRDY & ADC_ISR_ADRDY_Msk != 1) {}
SET_BIT(ADC2->ISR, ADC_ISR_ADRDY_Msk);
/********************ADC RES*****************************/
//SET_BIT(ADC2->CFGR, ADC_CFGR_RES_2 | ADC_CFGR_RES_1);
CLEAR_BIT(ADC2->CFGR, ADC_CFGR_RES_0 | ADC_CFGR_RES_1 | ADC_CFGR_RES_2);
/********************ADC Data Management*****************/
SET_BIT(ADC2->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1);//DMA Circular mode
/********************OVRMODE*****************************/
SET_BIT(ADC2->CFGR, ADC_CFGR_OVRMOD_Msk); //Erase old data
/********************CONT/Single/Discont*****************/
CLEAR_BIT(ADC2->CFGR, ADC_CFGR_DISCEN_Msk); // discontinuous mode
CLEAR_BIT(ADC2->CFGR, ADC_CFGR_CONT_Msk); // | ADC_CFGR_DISCEN_Msk
/***********************First to be converted**************/
//SET_BIT(ADC2->SQR1, ADC_SQR1_SQ1_0);
/********************Trigger Detection*******************/
SET_BIT(ADC2->CFGR, ADC_CFGR_EXTEN_0 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_3);//Trig rising edge TRGO2
CLEAR_BIT(ADC2->CFGR, ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTSEL_0 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_4);
/********************INput Preselection******************/
SET_BIT(ADC2->PCSEL, ADC_PCSEL_PCSEL_0);//Chan 0
/********************Sample Time reg*********************/
SET_BIT(ADC2->SMPR1, ADC_SMPR1_SMP0_0); //2.5 CLCK Cycles
/********************ADC IT******************************/
// SET_BIT(ADC2->IER, ADC_IER_EOCIE_Msk | ADC_IER_EOSMPIE_Msk | ADC_IER_OVRIE_Msk );//| ADC_IER_EOSIE_Msk | ADC_IER_OVRIE_Msk
// NVIC_EnableIRQ(ADC_IRQn);
// NVIC_SetVector(ADC_IRQn, (uint32_t)&ADC_IRQHandler);
}






