Hi! I'd would interface my Atmel to an another chip that uses a 3v3 logic levels of the I2C standard. I found a lot of methods to doing this.
One of them is the level shifter, or transistor logic shifter.
The circuit is the following: http://tangentsoft.net/elec/bitmaps/i2c-level-shifter.png
I don't understand when the 3v3 section goes to GND due to three state: in this case, with MOS active, the 5V (or slightly less than this) will be saw by the 3v3 part, exceeding the 3,3V maximum admitted voltage. The same when opposite: on 5V section I will see 3V. What I don't understand?
thexeno:
Hi! I'd would interface my Atmel to an another chip that uses a 3v3 logic levels of the I2C standard. I found a lot of methods to doing this.
One of them is the level shifter, or transistor logic shifter.
The circuit is the following: http://tangentsoft.net/elec/bitmaps/i2c-level-shifter.png
I don't understand when the 3v3 section goes to GND due to three state: in this case, with MOS active, the 5V (or slightly less than this) will be saw by the 3v3 part, exceeding the 3,3V maximum admitted voltage. The same when opposite: on 5V section I will see 3V. What I don't understand?